1461 search results - page 111 / 293 » Comparing the Optimal Performance of Parallel Architectures |
133
Voted
IPPS
1997
IEEE
15 years 7 months ago
1997
IEEE
Several optimizations to the Time Warp synchronization protocol for parallel discrete event simulation have been proposed and studied. Many of these optimizations have included so...
150
Voted
WMPI
2004
ACM
15 years 8 months ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
139
Voted
ASAP
2008
IEEE
15 years 9 months ago
2008
IEEE
Many complex systems require the use of floating point arithmetic that is exceedingly time consuming to perform on personal computers. However, floating point operators are also h...
130
click to vote
MSS
2003
IEEE
15 years 8 months ago
2003
IEEE
: Several solutions have been developed to provide dataintensive applications with the highest possible data rates. Such solutions tried to utilize the available network resources ...
266
Voted
FCCM
2011
IEEE
14 years 7 months ago
2011
IEEE
—The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this pap...