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» Comparing the Optimal Performance of Parallel Architectures
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ITNG
2007
IEEE
15 years 9 months ago
On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture
In this paper, we present several enhanced network techniques which are appropriate for VLSI implementation and have reduced complexity, high throughput, and simple routing algori...
Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh
IPPS
2006
IEEE
15 years 9 months ago
A study of the on-chip interconnection network for the IBM Cyclops64 multi-core architecture
The designs of high-performance processor architectures are moving toward the integration of a large number of multiple processing cores on a single chip. The IBM Cyclops-64 (C64)...
Yingping Zhang, Taikyeong Jeong, Fei Chen, Haiping...
122
Voted
CLUSTER
2004
IEEE
15 years 7 months ago
An efficient end-host architecture for cluster communication
Cluster computing environments built from commodity hardware have provided a cost-effective solution for many scientific and high-performance applications. Likewise, middleware te...
Xin Qi, Gabriel Parmer, Richard West
156
Voted
ASPLOS
2010
ACM
15 years 8 months ago
An asymmetric distributed shared memory model for heterogeneous parallel systems
Heterogeneous computing combines general purpose CPUs with accelerators to efficiently execute both sequential control-intensive and data-parallel phases of applications. Existin...
Isaac Gelado, Javier Cabezas, Nacho Navarro, John ...
ISCAS
2008
IEEE
287views Hardware» more  ISCAS 2008»
15 years 9 months ago
A high speed word level finite field multiplier using reordered normal basis
— Reordered normal basis is a certain permutation of a type II optimal normal basis. In this paper, a high speed design of a word level finite field multiplier using reordered ...
Ashkan Hosseinzadeh Namin, Huapeng Wu, Majid Ahmad...