Sciweavers

1461 search results - page 124 / 293
» Comparing the Optimal Performance of Parallel Architectures
Sort
View
119
Voted
DATE
2006
IEEE
100views Hardware» more  DATE 2006»
15 years 9 months ago
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simu...
Luciano Bononi, Nicola Concer
ASAP
2003
IEEE
113views Hardware» more  ASAP 2003»
15 years 8 months ago
A VLSI Architecture for Advanced Video Coding Motion Estimation
With the advent of new video standards such as MPEG-4 part-10 and H.264/H.26L, demands for advanced video coding (AVC), particularly in area of variable block searching motion est...
Swee Yeow, John V. McCanny
99
Voted
SBACPAD
2005
IEEE
112views Hardware» more  SBACPAD 2005»
15 years 9 months ago
Cooperation of Neighboring PEs in Clustered Architectures
Clustered architectures which intend to process data within a localized PE are one of the approaches to increase the performance under the difficulties of the wire delay problems...
Yukinori Sato, Ken-ichi Suzuki, Tadao Nakamura
ISCA
1994
IEEE
129views Hardware» more  ISCA 1994»
15 years 7 months ago
Impact of Sharing-Based Thread Placement on Multithreaded Architectures
Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interfere...
Radhika Thekkath, Susan J. Eggers
ICS
2010
Tsinghua U.
15 years 1 months ago
Decomposable and responsive power models for multicore processors using performance counters
Abstract—Power modeling based on performance monitoring counters (PMCs) has attracted the interest of many researchers since it become a quick approach to understand and analyse ...
Ramon Bertran, Marc González, Xavier Martor...