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» Comparing the Optimal Performance of Parallel Architectures
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DATE
2005
IEEE
113views Hardware» more  DATE 2005»
15 years 9 months ago
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures
With new sophisticated compiler technology, it is possible to schedule distant instructions efficiently. As a consequence, the amount of exploitable instruction level parallelism...
Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda...
IEEEPACT
2006
IEEE
15 years 9 months ago
Whole-program optimization of global variable layout
On machines with high-performance processors, the memory system continues to be a performance bottleneck. Compilers insert prefetch operations and reorder data accesses to improve...
Nathaniel McIntosh, Sandya Mannarswamy, Robert Hun...
HPDC
1997
IEEE
15 years 7 months ago
PARDIS: A Parallel Approach to CORBA
This paper describes PARDIS, a system containing explicit support for interoperability of PARallel DIStributed applications. PARDIS is based on the Common Object Request Broker Ar...
Katarzyna Keahey, Dennis Gannon
115
Voted
CDC
2008
IEEE
159views Control Systems» more  CDC 2008»
15 years 10 months ago
Incorporating drivability metrics into optimal energy management strategies for Hybrid Vehicles
— Hybrid Vehicle fuel economy performance is highly sensitive to the energy management strategy used to select among multiple energy sources. Optimal solutions are easy to specif...
Daniel F. Opila, Deepak Aswani, Ryan McGee, Jeffre...
ISCA
2010
IEEE
232views Hardware» more  ISCA 2010»
15 years 1 months ago
Evolution of thread-level parallelism in desktop applications
As the effective limits of frequency and instruction level parallelism have been reached, the strategy of microprocessor vendors has changed to increase the number of processing ...
Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mu...