1461 search results - page 145 / 293 » Comparing the Optimal Performance of Parallel Architectures |
147
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MICRO
2003
IEEE
15 years 8 months ago
2003
IEEE
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
138
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IPPS
2003
IEEE
15 years 8 months ago
2003
IEEE
Today, in many practical E-Commerce systems, the real stored data usually are short strings, such as names, addresses, or other information. Searching data within these short stri...
141
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ASPDAC
2001
ACM
15 years 7 months ago
2001
ACM
This paper deals with address assignment in code generation for digital signal processors (DSPs) with SIMD (single instruction multiple data) memory accesses. In these processors ...
97
Voted
CSB
2004
IEEE
15 years 7 months ago
2004
IEEE
We describe a novel hardware architecture for genomic and proteomic sequence alignment which achieves a speed-up of two to three orders of magnitude over Smith-Waterman dynamic pr...
133
Voted
ASPLOS
1989
ACM
15 years 7 months ago
1989
ACM
A very long instruction word (VLIW) processorexploits parallelism by controlling multiple operations in a single instruction word. This paper describes the architecture and compil...