1461 search results - page 14 / 293 » Comparing the Optimal Performance of Parallel Architectures |
138
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HPDC
2000
IEEE
15 years 7 months ago
2000
IEEE
We describe a software architecture for storage services in computational grid environments. Based upon a lightweight message-passing paradigm, the architecture enables the provis...
150
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ICPP
1998
IEEE
15 years 7 months ago
1998
IEEE
Exploiting locality at run-time is a complementary approach to a compiler approach for those applications with dynamic memory access patterns. This paper proposes a memory-layout ...
156
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FPL
2006
Springer
15 years 7 months ago
2006
Springer
Field programmable gate arrays (FPGAs), graphics processing units (GPUs) and Sony's PlayStation 2 vector units offer scope for hardware acceleration of applications. We compa...
121
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ICS
2009
Tsinghua U.
15 years 10 months ago
2009
Tsinghua U.
Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture...
130
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IEEEPACT
2000
IEEE
15 years 7 months ago
2000
IEEE
Region-based compilation repartitions a program into more desirable compilation units for optimization and scheduling, particularly beneficial for ILP architectures. With region-...