1461 search results - page 151 / 293 » Comparing the Optimal Performance of Parallel Architectures |
133
Voted
HPCA
1996
IEEE
15 years 7 months ago
1996
IEEE
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded process...
123
Voted
TWC
2008
15 years 3 months ago
2008
Abstract-- The V-BLAST (vertical Bell Labs layered Space-Time) architecture involves independent coding/decoding per antenna (layer) with equal rate and power per antenna and a fix...
115
Voted
ASAP
2003
IEEE
15 years 8 months ago
2003
IEEE
Recently, a number of researchers have started to investigate new video-on-demand (VoD) architectures using batching, patching and periodic broadcasting. These architectures, comp...
124
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HPCA
2007
IEEE
16 years 3 months ago
2007
IEEE
3D integration technology greatly increases transistor density while providing faster on-chip communication. 3D implementations of processors can simultaneously provide both laten...
134
Voted
ICDCS
2009
IEEE
15 years 10 months ago
2009
IEEE
Though plenty of research has been conducted to improve Internet P2P streaming quality perceived by endusers, little has been known about the upper bounds of achievable performanc...