Sciweavers

1461 search results - page 158 / 293
» Comparing the Optimal Performance of Parallel Architectures
Sort
View
HPCA
2008
IEEE
16 years 3 months ago
An OS-based alternative to full hardware coherence on tiled CMPs
The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling...
Christian Fensch, Marcelo Cintra
PODS
2004
ACM
128views Database» more  PODS 2004»
16 years 3 months ago
Replicated Declustering of Spatial Data
The problem of disk declustering is to distribute data among multiple disks to reduce query response times through parallel I/O. A strictly optimal declustering technique is one t...
Hakan Ferhatosmanoglu, Aravind Ramachandran, Ali S...
140
Voted
SIPS
2006
IEEE
15 years 9 months ago
Automated Architectural Exploration for Signal Processing Algorithms
Abstract— This paper presents a design environment for efficiently generating application-specific Intellectual Property (IP) cores for system level signal processing algorithm...
Ramsey Hourani, Ravi Jenkal, W. Rhett Davis, Winse...
ASPLOS
2008
ACM
15 years 5 months ago
SoftSig: software-exposed hardware signatures for code analysis and optimization
Many code analysis techniques for optimization, debugging, or parallelization need to perform runtime disambiguation of sets of addresses. Such operations can be supported efficie...
James Tuck, Wonsun Ahn, Luis Ceze, Josep Torrellas
138
Voted
SEMWEB
2010
Springer
15 years 1 months ago
Optimizing Enterprise-Scale OWL 2 RL Reasoning in a Relational Database System
OWL 2 RL was standardized as a less expressive but scalable subset of OWL 2 that allows a forward-chaining implementation. However, building an enterprise-scale forward-chaining ba...
Vladimir Kolovski, Zhe Wu, George Eadon