1461 search results - page 174 / 293 » Comparing the Optimal Performance of Parallel Architectures |
113
Voted
SIGGRAPH
1999
ACM
15 years 8 months ago
1999
ACM
Bus traffic between the graphics subsystem and memory can become a bottleneck when rendering geometrically complex meshes. In this paper, we investigate the use of vertex caching...
149
Voted
ISLPED
2004
ACM
15 years 9 months ago
2004
ACM
This paper presents a delay optimal FPGA clustering algorithm targeting low power. We assume that the configurable logic blocks of the FPGA can be programmed using either a high s...
141
Voted
COMSWARE
2007
IEEE
15 years 10 months ago
2007
IEEE
— Cache and Forward (CNF) Architecture is a novel architecture aimed at delivering content efficiently to potentially large number of intermittently connected mobile hosts. It us...
145
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VLSID
2002
IEEE
16 years 4 months ago
2002
IEEE
Compare CMOS Logic with Pass-Transistor Logic, a question was raised in our mind: "Does any rule exist that contains all good?" This paper reveals novel logic synthesis ...
144
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ICCAD
2009
IEEE
15 years 1 months ago
2009
IEEE
Multi-core processors have become an integral part of mainstream high performance computer systems. In parallel, exponentially increasing power density and packaging costs have ne...