1461 search results - page 188 / 293 » Comparing the Optimal Performance of Parallel Architectures |
103
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IPPS
2002
IEEE
15 years 8 months ago
2002
IEEE
The size and complexity of current custom VLSI have forced the use of high-level programming languages to describe hardware, and compiler and synthesis technology bstract designs ...
129
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VLSID
2002
IEEE
16 years 4 months ago
2002
IEEE
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
144
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FPGA
2008
ACM
15 years 5 months ago
2008
ACM
A design tool for routing channel segmentation in islandstyle FPGAs is presented. Given the FPGA architecture parameters and a set of benchmark designs, the tool optimizes routing...
120
Voted
GLOBECOM
2007
IEEE
15 years 10 months ago
2007
IEEE
—We study the resilience of MPLS flows over an agile all-photonic star WDM network (AAPN). On the basis of our previous inter-area optimal routing architecture, we propose and de...
134
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HIS
2008
15 years 5 months ago
2008
The performance of Artificial Neural Networks is largely influenced by the value of their parameters. Among these free parameters, one can mention those related with the network a...