1461 search results - page 208 / 293 » Comparing the Optimal Performance of Parallel Architectures |
136
Voted
TOG
2008
15 years 3 months ago
2008
We present an algorithm for constructing kd-trees on GPUs. This algorithm achieves real-time performance by exploiting the GPU's streaming architecture at all stages of kd-tr...
122
Voted
DAC
2005
ACM
16 years 4 months ago
2005
ACM
The race conditions often limit the smallest feasible clock period that the optimal clock skew scheduling can achieve. Therefore, the combination of clock skew scheduling and dela...
121
Voted
DAC
2004
ACM
16 years 4 months ago
2004
ACM
We present a set of techniques for placement-coupled, timingdriven logic replication. Two components are at the core of the approach. First is an algorithm for optimal timingdrive...
124
Voted
SAMOS
2004
Springer
15 years 9 months ago
2004
Springer
In this paper we present a new approach for generating high-speed optimized event-driven register transfer level (RTL) compiled simulators. The generation of the simulators is part...
188
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HPCA
2003
IEEE
16 years 4 months ago
2003
IEEE
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...