1461 search results - page 219 / 293 » Comparing the Optimal Performance of Parallel Architectures |
117
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WSC
1997
15 years 3 months ago
1997
We present a novel adaptive synchronization algorithm, called the minimum average cost (MAC) algorithm, in the context of the ParaSol parallel simulation system. ParaSol is a mult...
95
Voted
MICRO
2006
IEEE
15 years 8 months ago
2006
IEEE
With the trend towards increasing number of processor cores in future chip architectures, scalable directory-based protocols for maintaining cache coherence will be needed. Howeve...
107
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HPCA
2009
IEEE
16 years 2 months ago
2009
IEEE
As the last-level on-chip caches in chip-multiprocessors increase in size, the physical locality of on-chip data becomes important for delivering high performance. The non-uniform...
143
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ACMSE
2004
ACM
15 years 7 months ago
2004
ACM
Modern processors include features such as deep pipelining, multilevel cache hierarchy, branch predictors, out of order execution engine, and advanced floating point and multimedi...
143
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DAC
2006
ACM
16 years 2 months ago
2006
ACM
In this paper we propose a new communication synthesis approach targeting systems with sequential communication media (SCM). Since SCMs require that the reading sequence and writi...