1461 search results - page 227 / 293 » Comparing the Optimal Performance of Parallel Architectures |
104
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HPCA
2008
IEEE
16 years 2 months ago
2008
IEEE
Power-Efficient DRAM Speculation (PEDS) is a power optimization targeted at broadcast-based sharedmemory multiprocessor systems that speculatively access DRAM in parallel with the...
105
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ICPP
2003
IEEE
15 years 7 months ago
2003
IEEE
The bus that connects processors to memory is known to be a major architectural bottleneck in SMPs. However, both software and scheduling policies for these systems generally focu...
112
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BMCBI
2010
15 years 2 months ago
2010
Background: The selection of genes that discriminate disease classes from microarray data is widely used for the identification of diagnostic biomarkers. Although various gene sel...
140
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DAC
2010
ACM
15 years 2 months ago
2010
ACM
The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the per...
239
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POPL
2007
ACM
16 years 2 months ago
2007
ACM
Constraint Handling Rules (CHR) is a concurrent committedchoice constraint logic programming language to describe transformations (rewritings) among multi-sets of constraints (ato...