1461 search results - page 233 / 293 » Comparing the Optimal Performance of Parallel Architectures |
128
click to vote
DATE
2010
IEEE
15 years 7 months ago
2010
IEEE
—Multi-Processor System-on-Chips (MPSoCs) exploit task-level parallelism to achieve high computation throughput, but concurrent memory accesses from multiple PEs may cause memory...
121
click to vote
TVLSI
2010
14 years 8 months ago
2010
In many applications, a reduction of the amount of the original data or a representation of the original data by a small set of variables is often required. Among many techniques, ...
128
click to vote
ICDCSW
2003
IEEE
15 years 7 months ago
2003
IEEE
To obtain good performance in messaging over mobile networks, we have developed a Gateway. Gateway is a message hub that transmits information using store-and-forward messaging an...
154
click to vote
ICRA
1995
IEEE
15 years 5 months ago
1995
IEEE
This paper describes and evaluates an efficient technique that allows the fast generation of 3D triangular meshes from range images avoiding optimization procedures. Such a tool ...
110
click to vote
DAC
2005
ACM
16 years 2 months ago
2005
ACM
We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...