1461 search results - page 240 / 293 » Comparing the Optimal Performance of Parallel Architectures |
DAC
2008
ACM
16 years 26 days ago
2008
ACM
Daedalus is a system-level design flow for the design of multiprocessor system-on-chip (MP-SoC) based embedded multimedia systems. It offers a fully integrated tool-flow in which ...
101
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LCTRTS
2007
Springer
15 years 6 months ago
2007
Springer
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
108
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HPCA
2001
IEEE
16 years 7 days ago
2001
IEEE
fipical translation lookaside buffers (TLBs)can map a far smaller region of memory than application footprints demand, and the cost of handling TLB misses therefore limits the per...
IEEEPACT
2008
IEEE
15 years 6 months ago
2008
IEEE
We design and implement Mars, a MapReduce framework, on graphics processors (GPUs). MapReduce is a distributed programming framework originally proposed by Google for the ease of ...
MICRO
2007
IEEE
15 years 6 months ago
2007
IEEE
This paper describes FAST, a novel simulation methodology that can produce simulators that (i) are orders of magnitude faster than comparable simulators, (ii) are cycleaccurate, (...