1461 search results - page 38 / 293 » Comparing the Optimal Performance of Parallel Architectures |
114
Voted
SIGMETRICS
2010
ACM
15 years 6 months ago
2010
ACM
—Parallelism has often been used to improve the reliability and efficiency of a variety of different engineering systems. In this paper, we quantify the efficiency of paralleli...
87
Voted
DAC
1999
ACM
16 years 2 months ago
1999
ACM
Partitioning and clustering are crucial steps in circuit layout for handling large scale designs enabled by the deep submicron technologies. Retiming is an important sequential lo...
105
Voted
ISCA
2008
IEEE
15 years 8 months ago
2008
IEEE
In a chip-multiprocessor (CMP) system, the DRAM system is shared among cores. In a shared DRAM system, requests from a thread can not only delay requests from other threads by cau...
TCAD
2002
15 years 1 months ago
2002
Abstract--In this paper, we study wire width planning for interconnect performance optimization in an interconnect-centric design flow. We first propose some simplified, yet near-o...
118
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ISPA
2007
Springer
15 years 8 months ago
2007
Springer
The Cell processor is a typical example of a heterogeneous multiprocessor-on-chip architecture that uses several levels of parallelism to deliver high performance. Closing the gap ...