1461 search results - page 40 / 293 » Comparing the Optimal Performance of Parallel Architectures |
100
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TVLSI
2008
15 years 1 months ago
2008
Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fi...
110
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DATE
2003
IEEE
15 years 7 months ago
2003
IEEE
We propose a new metric for evaluation of interconnect architectures. This metric is computed by optimal assignment of wires from a given wire length distribution (WLD) to a given...
126
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PAAPP
2002
15 years 1 months ago
2002
Abstract. The performance of shared-memory (OpenMP) implementations of three different PDE solver kernels representing finite difference methods, finite volume methods, and spectra...
158
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VLSID
2001
IEEE
16 years 2 months ago
2001
IEEE
The emergence of several communication architectures for System-on-Chips provides designers with a variety of design alternatives. In addition, the need to customize the system ar...
101
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HPCA
2005
IEEE
16 years 2 months ago
2005
IEEE
Memory system optimizations have been well studied on single-threaded systems; however, the wide use of simultaneous multithreading (SMT) techniques raises questions over their ef...