1461 search results - page 52 / 293 » Comparing the Optimal Performance of Parallel Architectures |
120
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IPPS
1996
IEEE
15 years 6 months ago
1996
IEEE
Multiple instruction issue processors place high demands on register file bandwidth. One solution to reduce this bottleneck is the use of multiple register files. Register allocat...
107
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IPPS
2009
IEEE
15 years 8 months ago
2009
IEEE
In this paper we use Dijkstra’s algorithm as a challenging, hard to parallelize paradigm to test the efficacy of several parallelization techniques in a multicore architecture....
116
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HPCA
2008
IEEE
16 years 2 months ago
2008
IEEE
In this paper, we propose Runahead Threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in Simultaneous Multithreaded...
123
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ICCD
2008
IEEE
15 years 10 months ago
2008
IEEE
—One of the major design verification challenges in the development of Anton, a massively parallel special-purpose machine for molecular dynamics, was to provide evidence that co...
107
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DAC
2005
ACM
15 years 3 months ago
2005
ACM
Automated analog sizing is becoming an unavoidable solution for increasing analog design productivity. The complexity of typical analog SoC subsystems however calls for efficient ...