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» Comparing the Optimal Performance of Parallel Architectures
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CASES
2006
ACM
15 years 7 months ago
Integrated scratchpad memory optimization and task scheduling for MPSoC architectures
Multiprocessor system-on-chip (MPSoC) is an integrated circuit containing multiple instruction-set processors on a single chip that implements most of the functionality of a compl...
Vivy Suhendra, Chandrashekar Raghavan, Tulika Mitr...
IPPS
2008
IEEE
15 years 8 months ago
DC-SIMD : Dynamic communication for SIMD processors
SIMD (single instruction multiple data)-type processors have been found very efficient in image processing applications, because their repetitive structure is able to exploit the...
Raymond Frijns, Hamed Fatemi, Bart Mesman, Henk Co...
MICRO
2008
IEEE
107views Hardware» more  MICRO 2008»
15 years 8 months ago
A distributed processor state management architecture for large-window processors
— Processor architectures with large instruction windows have been proposed to expose more instruction-level parallelism (ILP) and increase performance. Some of the proposed arch...
Isidro Gonzalez, Marco Galluzzi, Alexander V. Veid...
120
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ISPAN
2000
IEEE
15 years 6 months ago
Versatile Processor Design for Efficiency and High Performance
We present new architectural concepts for uniprocessor designs that conform to the data-driven computation paradigm. Usage of our D2 -CPU (Data-Driven processor) follows the natura...
Sotirios G. Ziavras
ICS
2009
Tsinghua U.
14 years 11 months ago
Efficient high performance collective communication for the cell blade
This paper presents high-performance collective communication algorithms and implementations that exploit the unique architectural features of the Cell heterogeneous multicore pro...
Qasim Ali, Samuel P. Midkiff, Vijay S. Pai