Sciweavers

1461 search results - page 58 / 293
» Comparing the Optimal Performance of Parallel Architectures
Sort
View
96
Voted
EUROPAR
1999
Springer
15 years 6 months ago
An Evaluation of High Performance Fortran Compilers Using the HPFBench Benchmark Suite
Abstract. The High Performance Fortran (HPF) benchmark suite HPFBench was designed for evaluating the HPF language and compilers on scalable architectures. The functionality of the...
Guohua Jin, Y. Charlie Hu
120
Voted
IPPS
2002
IEEE
15 years 6 months ago
Effective Cross-Platform, Multilevel Parallelism via Dynamic Adaptive Execution
This paper presents preliminary efforts to develop compilation and execution environments that achieve performance portability of multilevel parallelization on hierarchical archit...
Walden Ko, Mark N. Yankelevsky, Dimitrios S. Nikol...
VLSISP
2008
132views more  VLSISP 2008»
15 years 1 months ago
Serial and Parallel FPGA-based Variable Block Size Motion Estimation Processors
H.264/AVC is the latest video coding standard adopting variable block size motion estimation (VBS-ME), quarter-pixel accuracy, motion vector prediction and multi-reference frames f...
Brian M. H. Li, Philip Heng Wai Leong
SBACPAD
2003
IEEE
106views Hardware» more  SBACPAD 2003»
15 years 7 months ago
A Parallel Implementation of the LTSn Method for a Radiative Transfer Problem
— A radiative transfer solver that implements the LTSn method was optimized and parallelized using the MPI message passing communication library. Timing and profiling informatio...
Roberto P. Souto, Haroldo F. de Campos Velho, Step...
IEEEPACT
2000
IEEE
15 years 6 months ago
Exploring the Limits of Sub-Word Level Parallelism
Multimedia instruction set extensions have become a prominent feature in desktop microprocessor platforms, promising superior performance on a wide range of floating-point and int...
Kevin Scott, Jack W. Davidson