1461 search results - page 60 / 293 » Comparing the Optimal Performance of Parallel Architectures |
117
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RSP
2005
IEEE
15 years 7 months ago
2005
IEEE
Nowadays, Architecture Description Languages (ADLs) are getting popular to speed up the development of complex SoC design, by performing the design space explon a higher level of ...
ICCAD
2007
IEEE
15 years 10 months ago
2007
IEEE
Late CMOS scaling reduces device reliability, and existing work has studied the permanent SER (soft error rate) for configuration memory in FPGA extensively. In this paper, we sh...
122
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FCCM
2006
IEEE
15 years 8 months ago
2006
IEEE
Abstract— This paper introduces a novel architecture for performing the core computations required by dynamic programming (DP) techniques. The latter pertain to a vast range of a...
120
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HPCA
2003
IEEE
16 years 2 months ago
2003
IEEE
To continue to improve processor performance, microarchitects seek to increase the effective instruction level parallelism (ILP) that can be exploited in applications. A fundament...
120
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IEEEPACT
2002
IEEE
15 years 6 months ago
2002
IEEE
In this paper, we describe an algorithm and implementation of locality optimizations for architectures with instruction sets such as Intel’s SSE and Motorola’s AltiVec that su...