1461 search results - page 93 / 293 » Comparing the Optimal Performance of Parallel Architectures |
134
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ICCS
2009
Springer
15 years 8 months ago
2009
Springer
The development of optimized codes is time-consuming and requires extensive architecture, compiler, and language expertise, therefore, computational scientists are often forced to ...
119
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IPPS
2006
IEEE
15 years 8 months ago
2006
IEEE
In this paper, we present a dynamically reconfigurable cache architecture using adaptive block allocation policy analyzed by means of simulation. Our main objectives are: to propo...
112
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PDCAT
2004
Springer
15 years 7 months ago
2004
Springer
Abstract. This paper proposes a simplified simultaneous multithreading (SMT) architecture aiming at CPU cores of embedded SoCs for consumer applications. This architecture reduces...
ISCA
1997
IEEE
15 years 6 months ago
1997
IEEE
DataScalar architectures improve memory system performance by running computation redundantly across multiple processors, which are each tightly coupled with an associated memory....
121
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IPPS
2002
IEEE
15 years 7 months ago
2002
IEEE
Multiple memory module architecture enjoys higher memory access bandwidth and thus higher performance. Two key problems in gaining high performance in this kind of architecture ar...