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ISLPED
2010
ACM
193views Hardware» more  ISLPED 2010»
14 years 10 months ago
PASAP: power aware structured ASIC placement
Structured ASICs provide an exciting middle ground between FPGA and ASIC design methodologies. Compared to ASIC, structured ASIC based designs require lower non recurring engineer...
Ashutosh Chakraborty, David Z. Pan
ISER
2000
Springer
88views Robotics» more  ISER 2000»
15 years 1 months ago
Design, Implementation, and Remote Operation of the Humanoid H6
Abstract: The paper describes the humanoid robot \H6", which was designed to serve as a platform for experimental research on the development of advanced humanoid-type robots....
Satoshi Kagami, Koichi Nishiwaki, James J. Kuffner...
OSDI
2008
ACM
15 years 10 months ago
A Comparison of High-Level Full-System Power Models
Dynamic power management in enterprise environments requires an understanding of the relationship between resource utilization and system-level power consumption. Power models bas...
Suzanne Rivoire, Parthasarathy Ranganathan, Christ...
ASPDAC
2008
ACM
83views Hardware» more  ASPDAC 2008»
14 years 12 months ago
Run-time power gating of on-chip routers using look-ahead routing
Since on-chip routers in Network-on-Chips play a key role in on-chip communication between cores, they should be always preparing for packet injections even if a part of cores are ...
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Ama...
ICCD
2002
IEEE
110views Hardware» more  ICCD 2002»
15 years 6 months ago
Branch Predictor Prediction: A Power-Aware Branch Predictor for High-Performance Processors
We introduce Branch Predictor Prediction (BPP) as a power-aware branch prediction technique for high performance processors. Our predictor reduces branch prediction power dissipat...
Amirali Baniasadi, Andreas Moshovos