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DAC
2005
ACM
14 years 12 months ago
Sign bit reduction encoding for low power applications
This paper proposes a low power technique, called SBR (Sign Bit Reduction) which may reduce the switching activity in multipliers as well as data buses. Utilizing the multipliers ...
M. Saneei, Ali Afzali-Kusha, Zainalabedin Navabi
ICESS
2004
Springer
15 years 3 months ago
The Modeling for Dynamic Power Management of Embedded Systems
In this paper we present a new modeling technique using software engineering tool Flow Model for modeling and solving the Dynamic Power Management (DPM) with complex behavioral cha...
Jiangwei Huang, Tianzhou Chen, Minjiao Ye, Yi Lian
IOR
2006
118views more  IOR 2006»
14 years 10 months ago
A Stochastic Programming Approach to Power Portfolio Optimization
The DASH model for Power Portfolio Optimization provides a tool which helps decision-makers coordinate production decisions with opportunities in the wholesale power market. The m...
Suvrajeet Sen, Lihua Yu, Talat Genc
ASAP
2009
IEEE
98views Hardware» more  ASAP 2009»
14 years 7 months ago
A Power-Scalable Switch-Based Multi-processor FFT
This paper examines the architecture, algorithm and implementation of a switch-based multi-processor realization of the fast Fourier transform (FFT). The architecture employs M pr...
Bassam Jamil Mohd, Earl E. Swartzlander Jr.
ICCAD
2007
IEEE
157views Hardware» more  ICCAD 2007»
15 years 6 months ago
Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture
—In this paper, we introduce a novel reconfigurable architecture, named 3D nFPGA, which utilizes 3D integration techniques and new nanoscale materials synergistically. The propos...
Chen Dong, Deming Chen, Sansiri Tanachutiwat, Wei ...