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ISCAS
2002
IEEE
141views Hardware» more  ISCAS 2002»
15 years 9 months ago
Power characterization of digital filters implemented on FPGA
The evaluation of power consumption in complex digital systems is a hard task that normally requires long simulation time and complicated models. In this work, we obtain power con...
Gian-Carlo Cardarilli, Andrea Del Re, Alberto Nann...
ISQED
2000
IEEE
91views Hardware» more  ISQED 2000»
15 years 8 months ago
Probabilistic Bottom-Up RTL Power Estimation
We address the problem of power estimation at the register-transfer level (RTL). At this level, the circuit is described in terms of a set of interconnected memory elements and co...
Ricardo Ferreira, A.-M. Trullemans, José C....
CHES
2006
Springer
74views Cryptology» more  CHES 2006»
15 years 8 months ago
Optically Enhanced Position-Locked Power Analysis
Abstract. This paper introduces a refinement of the power-analysis attack on integrated circuits. By using a laser to illuminate a specific area on the chip surface, the current th...
Sergei P. Skorobogatov
DDECS
2007
IEEE
101views Hardware» more  DDECS 2007»
15 years 4 months ago
A Low Noise and Low Power CMOS Image Sensor with Pixel-level Correlated Double Sampling
—A Low noise and low power CMOS Image Sensor (CIS) with pixel-level Correlated Double Sampling (CDS) is proposed. As the pixel readout circuit using source follower is major read...
Dongsoo Kim, Gunhee Han
CAL
2006
15 years 4 months ago
Performance, power efficiency and scalability of asymmetric cluster chip multiprocessors
This paper evaluates asymmetric cluster chip multiprocessor (ACCMP) architectures as a mechanism to achieve the highest performance for a given power budget. ACCMPs execute serial ...
T. Y. Morad, Uri C. Weiser, A. Kolodnyt, Mateo Val...