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HICSS
2010
IEEE
193views Biometrics» more  HICSS 2010»
15 years 11 months ago
The Topological and Electrical Structure of Power Grids
Numerous recent papers have found important relationships between network structure and risks within networks. These results indicate that network structure can dramatically affec...
Paul Hines, Seth Blumsack, E. Cotilla Sanchez, C. ...
ISQED
2009
IEEE
133views Hardware» more  ISQED 2009»
15 years 11 months ago
A novel ACO-based pattern generation for peak power estimation in VLSI circuits
Estimation of maximal power consumption is an essential task in VLSI circuit realizations since power value significantly affects the reliability of the circuits. The key issue o...
Yi-Ling Liu, Chun-Yao Wang, Yung-Chih Chen, Ya-Hsi...
DAC
2006
ACM
16 years 5 months ago
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...
Yu Hu, Yan Lin, Lei He, Tim Tuan
PATMOS
2007
Springer
15 years 10 months ago
Optimization for Real-Time Systems with Non-convex Power Versus Speed Models
Abstract. Until now, the great majority of research in low-power systems has assumed a convex power model. However, recently, due to the confluence of emerging technological and ar...
Ani Nahapetian, Foad Dabiri, Miodrag Potkonjak, Ma...
MM
2005
ACM
157views Multimedia» more  MM 2005»
15 years 10 months ago
Chameleon: application level power management with performance isolation
In this paper, we present Chameleon—an application-level power management approach for reducing energy consumption in mobile processors. Our approach exports the entire responsi...
Xiaotao Liu, Prashant J. Shenoy, Mark D. Corner