3955 search results - page 240 / 791 » Comparing the Power of Robots |
140
click to vote
VLSID
2004
IEEE
16 years 6 months ago
2004
IEEE
{A new low-power design method produces CMOS circuits that consume the least dynamic power at the highest speed permitted under the technology constraint. A gate is characterized b...
169
click to vote
ISCA
2002
IEEE
15 years 10 months ago
2002
IEEE
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
157
click to vote
JETC
2008
15 years 4 months ago
2008
With aggressive reductions in feature sizes and the integration of multiple functionalities on the same die, bottlenecks due to I/O pin limitations have become a severe issue in to...
185
Voted
TWC
2010
15 years 17 days ago
2010
Abstract--In this paper we develop a new analytical methodology for the evaluation of the outage probability of cooperative decode-and-forward (DF) automatic-repeat-request (ARQ) r...
146
click to vote
DAC
2004
ACM
16 years 6 months ago
2004
ACM
timing analysis tools to replace standard deterministic static timing analyzers whereas [8,27] develop approaches for the statistical estimation of leakage power considering within...