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146
Voted
SOCC
2008
IEEE
15 years 11 months ago
2008
IEEE
In this paper a new ultra low power SRAM cell is proposed. In the proposed SRAM topology, additional circuitry has been added to a standard 6T-SRAM cell to improve the static nois...
116
Voted
ASYNC
2005
IEEE
15 years 10 months ago
2005
IEEE
We present an apparatus used to distribute a timing reference or clock across the extent of a digital system. Selftimed circuitry both generates and distributes a clock signal, wh...
97
Voted
ISCAS
2005
IEEE
15 years 10 months ago
2005
IEEE
In this paper, a framework of designing a low-error and power-efficient two’s-complement fixed-width Booth multiplier that receives two n-bit numbers and produces an n-bit produ...
135
Voted
SBCCI
2003
ACM
15 years 10 months ago
2003
ACM
– We present a new architecture for signed multiplication which maintains the pure form of an array multiplier, exhibiting a much lower overhead than the Booth architecture. This...
108
Voted
ASPDAC
1998
ACM
15 years 9 months ago
1998
ACM
-- The logic construction of a double-edge-triggered (DET) flip-flop, which can receive input signal at two levels of the clock, is analyzed and a new circuit design of CMOS DET fl...