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ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
15 years 11 months ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
174
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NOCS
2008
IEEE
15 years 11 months ago
Network Simplicity for Latency Insensitive Cores
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...
Daniel Gebhardt, JunBok You, W. Scott Lee, Kenneth...
QEST
2007
IEEE
15 years 10 months ago
A business-oriented load dispatching framework for online auction sites
Online auction sites have unique workloads and user behavior characteristics that do not exist in other e-commerce sites. Earlier studies by the authors identified i) significan...
Daniel A. Menascé, Vasudeva Akula
HIPC
2007
Springer
15 years 10 months ago
Self-optimization of Performance-per-Watt for Interleaved Memory Systems
- With the increased complexity of platforms coupled with data centers’ servers sprawl, power consumption is reaching unsustainable limits. Memory is an important target for plat...
Bithika Khargharia, Salim Hariri, Mazin S. Yousif
GLVLSI
2009
IEEE
143views VLSI» more  GLVLSI 2009»
15 years 8 months ago
Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO
In this paper, we present the design of a P4 (Power-PerformanceProcess-Parasitic) aware voltage controlled oscillator (VCO) at nanoCMOS technologies. Through simulations, we have ...
Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos