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116
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ICCD
2005
IEEE
101views Hardware» more  ICCD 2005»
16 years 18 days ago
Three-Dimensional Cache Design Exploration Using 3DCacti
As technology scales, interconnects dominate the performance and power behavior of deep submicron designs. Three-dimensional integrated circuits (3D ICs) have been proposed as a w...
Yuh-Fang Tsai, Yuan Xie, Narayanan Vijaykrishnan, ...
143
Voted
ICCD
2005
IEEE
165views Hardware» more  ICCD 2005»
16 years 18 days ago
Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation
Presently, Architecture Description Languages (ADLs) are widely used to raise the abstraction level of the design space exploration of Application Specific Instruction-set Proces...
Ernst Martin Witte, Anupam Chattopadhyay, Oliver S...
138
Voted
ICCD
2004
IEEE
119views Hardware» more  ICCD 2004»
16 years 18 days ago
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design
I/O placement has always been a concern in modern IC design. Due to flip-chip technology, I/O can be placed throughout the whole chip without long wires from the periphery of the...
Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzh...
126
Voted
ICCD
2004
IEEE
119views Hardware» more  ICCD 2004»
16 years 18 days ago
Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing
We present a method for incorporating crosstalk reduction criteria into global routing under an innovative power supply architecture, while considering the constraints imposed by ...
Tianpei Zhang, Sachin S. Sapatnekar
112
Voted
ICCD
2001
IEEE
84views Hardware» more  ICCD 2001»
16 years 18 days ago
Static Energy Reduction Techniques for Microprocessor Caches
Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of increased static energy consumption ...
Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, S...