143 search results - page 11 / 29 » Compiled hardware acceleration of Molecular Dynamics code |
ISCA
2005
IEEE
15 years 3 months ago
2005
IEEE
Instruction set customization is an effective way to improve processor performance. Critical portions of application dataflow graphs are collapsed for accelerated execution on s...
SIGGRAPH
1994
ACM
15 years 1 months ago
1994
ACM
This paper describes a methodology for using the matrix-vector multiply and scan conversion hardware present in many graphics workstations to rapidly approximate the optical flow ...
105
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ISCAS
1999
IEEE
15 years 1 months ago
1999
IEEE
In this paper, we present the application of dynamic trellis diagrams (DTDs) to automatic translation of data flow graphs (DFGs) into highly optimized programs for digital signal ...
110
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IEEEINTERACT
2003
IEEE
15 years 2 months ago
2003
IEEE
Recent studies on program execution behavior reveal that a large amount of execution time is spent in small frequently executed regions of code. Whereas adaptive cache management ...
ISPASS
2010
IEEE
15 years 4 months ago
2010
IEEE
—While many-core accelerator architectures, such as today’s Graphics Processing Units (GPUs), offer orders of magnitude more raw computing power than contemporary CPUs, their m...