143 search results - page 19 / 29 » Compiled hardware acceleration of Molecular Dynamics code |
MICRO
2003
IEEE
15 years 2 months ago
2003
IEEE
Traditional software controlled data cache prefetching is often ineffective due to the lack of runtime cache miss and miss address information. To overcome this limitation, we imp...
126
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IPPS
1997
IEEE
15 years 1 months ago
1997
IEEE
We present the Data Parallel Fortran (DPF) benchmark suite, a set of data parallel Fortran codes forevaluatingdata parallel compilers appropriatefor any target parallel architectu...
100
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ISCA
2006
IEEE
15 years 3 months ago
2006
IEEE
A Co-Designed Virtual Machine allows designers to implement a processor via a combination of hardware and software. Dynamic binary translation converts code written for a conventi...
95
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CGO
2005
IEEE
15 years 3 months ago
2005
IEEE
Software code caches are becoming ubiquitous, in dynamic optimizers, runtime tool platforms, dynamic translators, fast simulators and emulators, and dynamic compilers. Caching fre...
MICRO
2010
IEEE
14 years 7 months ago
2010
IEEE
Wide Single Instruction, Multiple Thread (SIMT) architectures often require a static allocation of thread groups that are executed in lockstep throughout the entire application ker...