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» Compiled hardware acceleration of Molecular Dynamics code
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TCAD
2008
127views more  TCAD 2008»
14 years 9 months ago
Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration
Abstract--Multimedia and DSP applications have several computationally intensive kernels which are often offloaded and accelerated by application-specific hardware. This paper pres...
Sejong Oh, Tag Gon Kim, Jeonghun Cho, Elaheh Bozor...
CODES
2006
IEEE
15 years 3 months ago
A multiprocessing approach to accelerate retargetable and portable dynamic-compiled instruction-set simulation
Traditionally, instruction-set simulators (ISS’s) are sequential programs running on individual processors. Besides the advances of simulation techniques, ISS’s have been main...
Wei Qin, Joseph D'Errico, Xinping Zhu
MICRO
2010
IEEE
175views Hardware» more  MICRO 2010»
14 years 7 months ago
Efficient Selection of Vector Instructions Using Dynamic Programming
Accelerating program performance via SIMD vector units is very common in modern processors, as evidenced by the use of SSE, MMX, VSE, and VSX SIMD instructions in multimedia, scien...
Rajkishore Barik, Jisheng Zhao, Vivek Sarkar
CGO
2007
IEEE
15 years 3 months ago
Exploiting Narrow Accelerators with Data-Centric Subgraph Mapping
The demand for high performance has driven acyclic computation accelerators into extensive use in modern embedded and desktop architectures. Accelerators that are ideal from a sof...
Amir Hormati, Nathan Clark, Scott A. Mahlke
BMCBI
2008
211views more  BMCBI 2008»
14 years 9 months ago
CUDA compatible GPU cards as efficient hardware accelerators for Smith-Waterman sequence alignment
Background: Searching for similarities in protein and DNA databases has become a routine procedure in Molecular Biology. The Smith-Waterman algorithm has been available for more t...
Svetlin Manavski, Giorgio Valle