Sciweavers

143 search results - page 8 / 29
» Compiled hardware acceleration of Molecular Dynamics code
Sort
View
HPCA
1997
IEEE
15 years 1 months ago
Architectural Support for Compiler-Synthesized Dynamic Branch Prediction Strategies: Rationale and Initial Results
This paper introduces a new architectural approach that supports compiler-synthesized dynamic branch predication. In compiler-synthesized dynamic branch prediction, the compiler g...
David I. August, Daniel A. Connors, John C. Gyllen...
MICRO
1999
IEEE
109views Hardware» more  MICRO 1999»
15 years 1 months ago
Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results
Recent studies on value locality reveal that many instructions are frequently executed with a small variety of inputs. This paper proposes an approach that integrates architecture...
Daniel A. Connors, Wen-mei W. Hwu
DATE
2009
IEEE
117views Hardware» more  DATE 2009»
15 years 4 months ago
Using dynamic compilation for continuing execution under reduced memory availability
—This paper explores the use of dynamic compilation for continuing execution even if one or more of the memory banks used by an application become temporarily unavailable (but th...
Ozcan Ozturk, Mahmut T. Kandemir
MICRO
1995
IEEE
72views Hardware» more  MICRO 1995»
15 years 1 months ago
Dynamic rescheduling: a technique for object code compatibility in VLIW architectures
Lack of object code compatibility in VLIW architectures is a severe limit to their adoption as a generalpurpose computing paradigm. Previous approaches include hardware and softwa...
Thomas M. Conte, Sumedh W. Sathaye
ICCD
2006
IEEE
157views Hardware» more  ICCD 2006»
15 years 6 months ago
Dynamic Co-Processor Architecture for Software Acceleration on CSoCs
By integrating one or more (hard or soft) CPU core on the chip, new generation platform FPGAs have become configurable systems on a chip (CSoC) that support a combined software an...
Abhishek Mitra, Zhi Guo, Anirban Banerjee, Walid A...