1338 search results - page 114 / 268 » Compiler Architectures for Heterogeneous Systems |
117
Voted
WSC
2001
15 years 5 months ago
2001
In models of military operations it is important to include the Command and Control (C2) process in order to achieve a realistic simulation of a military force's behaviour an...
114
Voted
HPCS
2006
IEEE
15 years 9 months ago
2006
IEEE
This paper presents the initial design of the Cyclops-64 (C64) system software infrastructure and tools under development as a joint effort between IBM T.J. Watson Research Center...
127
Voted
CC
2007
Springer
15 years 9 months ago
2007
Springer
This paper presents a compiler technique that reduces the energy consumption of the memory subsystem, for an off-chip partitioned memory architecture having multiple memory banks ...
141
Voted
ISCA
2005
IEEE
15 years 9 months ago
2005
IEEE
Instruction set customization is an effective way to improve processor performance. Critical portions of application dataflow graphs are collapsed for accelerated execution on s...
140
Voted
TPDS
2010
15 years 2 months ago
2010
—Thread-level parallelism (TLP) has been extensively studied in order to overcome the limitations of exploiting instruction-level parallelism (ILP) on high-performance superscala...