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JCISE
2002
166views more  JCISE 2002»
15 years 3 months ago
The STEP Modular Architecture
The first Technical Note in this series [1] introduced the international standard ISO 10303, informally known as STEP (STandard for the Exchange of Product model data). Subsequent...
Allison Barnard Feeney
ISCAS
2005
IEEE
166views Hardware» more  ISCAS 2005»
15 years 9 months ago
Extending SystemC to support mixed discrete-continuous system modeling and simulation
—Systems on chip are more and more heterogeneous and include software, analog/RF and digital hardware, and non-electronic components such as sensors or actuators. The design and ...
Alain Vachoux, Christoph Grimm, Karsten Einwich
SAMOS
2010
Springer
15 years 2 months ago
Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator
—Instruction set simulators (ISS) are vital tools for compiler and processor architecture design space exploration and verification. State-of-the-art simulators using just-in-ti...
Igor Böhm, Björn Franke, Nigel P. Topham
DAC
2000
ACM
16 years 4 months ago
The design and use of simplepower: a cycle-accurate energy estimation tool
In this paper, we presen t the design and use of a comprehensiv e framework, SimplePower, for evaluating the e ect of high-level algorithmic, architectural, and compilation tradeo...
Wu Ye, Narayanan Vijaykrishnan, Mahmut T. Kandemir...
VLSISP
2008
123views more  VLSISP 2008»
15 years 3 months ago
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...
Bingfeng Mei, Bjorn De Sutter, Tom Vander Aa, M. W...