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MICRO
2010
IEEE
156views Hardware» more  MICRO 2010»
14 years 10 months ago
Explicit Communication and Synchronization in SARC
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
Manolis Katevenis, Vassilis Papaefstathiou, Stamat...
VEE
2009
ACM
146views Virtualization» more  VEE 2009»
15 years 6 months ago
Demystifying magic: high-level low-level programming
r of high-level languages lies in their abstraction over hardware and software complexity, leading to greater security, better reliability, and lower development costs. However, o...
Daniel Frampton, Stephen M. Blackburn, Perry Cheng...
HIPEAC
2009
Springer
15 years 6 months ago
Collective Optimization
Abstract. Iterative compilation is an efficient approach to optimize programs on rapidly evolving hardware, but it is still only scarcely used in practice due to a necessity to gat...
Grigori Fursin, Olivier Temam
IWMM
2009
Springer
152views Hardware» more  IWMM 2009»
15 years 6 months ago
A new approach to parallelising tracing algorithms
Tracing algorithms visit reachable nodes in a graph and are central to activities such as garbage collection, marshalling etc. Traditional sequential algorithms use a worklist, re...
Cosmin E. Oancea, Alan Mycroft, Stephen M. Watt
102
Voted
RTAS
2005
IEEE
15 years 5 months ago
Bounding Worst-Case Data Cache Behavior by Analytically Deriving Cache Reference Patterns
While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and partic...
Harini Ramaprasad, Frank Mueller