118 search results - page 19 / 24 » Compiler Support for Exploiting Coarse-Grained Pipelined Par... |
CODES
2010
IEEE
14 years 7 months ago
2010
IEEE
The last years have shown that there is no way to disregard the advantages provided by multiprocessor System-on-Chip (MPSoC) architectures in the embedded systems domain. Using mu...
79
Voted
LCPC
2009
Springer
15 years 2 months ago
2009
Springer
The advent of multicores presents a promising opportunity for exploiting fine grained parallelism present in programs. Programs parallelized in the above fashion, typically involv...
ICS
2001
Tsinghua U.
15 years 2 months ago
2001
Tsinghua U.
Recent proposals for Chip Multiprocessors (CMPs) advocate speculative, or implicit, threading in which the hardware employs prediction to peel off instruction sequences (i.e., imp...
CODES
2007
IEEE
15 years 3 months ago
2007
IEEE
We address the problem of instruction selection for Multi-Output Instructions (MOIs), producing more than one result. Such inherently parallel hardware instructions are very commo...
IPPS
2005
IEEE
15 years 3 months ago
2005
IEEE
In this paper we explore a new clustering approach for reducing the complexity of wide issue in-order processors based on EPIC architectures. Complexity effectiveness is achieved ...