Sciweavers

199 search results - page 16 / 40
» Compiler Support for Reducing Leakage Energy Consumption
Sort
View
AC
2005
Springer
14 years 9 months ago
Power Analysis and Optimization Techniques for Energy Efficient Computer Systems
Reducing power consumption has become a major challenge in the design and operation of today's computer systems. This chapter describes different techniques addressing this c...
Wissam Chedid, Chansu Yu, Ben Lee
ICCAD
2009
IEEE
109views Hardware» more  ICCAD 2009»
14 years 7 months ago
Energy reduction for STT-RAM using early write termination
The emerging Spin Torque Transfer memory (STT-RAM) is a promising candidate for future on-chip caches due to STT-RAM's high density, low leakage, long endurance and high acce...
Ping Zhou, Bo Zhao, Jun Yang 0002, Youtao Zhang
75
Voted
MICRO
2005
IEEE
113views Hardware» more  MICRO 2005»
15 years 3 months ago
Thermal Management of On-Chip Caches Through Power Density Minimization
Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can b...
Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I....
MUM
2009
ACM
190views Multimedia» more  MUM 2009»
15 years 4 months ago
Handy feedback: connecting smart meters with mobile phones
Reducing their energy consumption has become an important objective for many people. Consumption transparency and timely feedback are essential to support those who want to adjust...
Markus Weiss, Friedemann Mattern, Tobias Graml, Th...
59
Voted
DATE
2009
IEEE
131views Hardware» more  DATE 2009»
15 years 4 months ago
Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling
this paper proposes a novel Process Variation Aware SRAM architecture designed to inherently support voltage scaling. The peripheral circuitry of the SRAM is modified to selectivel...
Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, F...