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ICCCN
2007
IEEE
15 years 5 months ago
An Energy-Efficient Scheduling Algorithm Using Dynamic Voltage Scaling for Parallel Applications on Clusters
In the past decade cluster computing platforms have been widely applied to support a variety of scientific and commercial applications, many of which are parallel in nature. Howev...
Xiaojun Ruan, Xiao Qin, Ziliang Zong, Kiranmai Bel...
ISQED
2006
IEEE
101views Hardware» more  ISQED 2006»
15 years 5 months ago
Compiler-Directed Power Density Reduction in NoC-Based Multi-Core Designs
As transistor counts keep increasing and clock frequencies rise, high power consumption is becoming one of the most important obstacles, preventing further scaling and performance...
Sri Hari Krishna Narayanan, Mahmut T. Kandemir, Oz...
SAC
2004
ACM
15 years 4 months ago
L0 buffer energy optimization through scheduling and exploration
Clustered L0 buffers are an interesting alternative to reduce energy consumption in the instruction memory hierarchy of embedded VLIW processors. Currently, the synthesis of L0 cl...
Murali Jayapala, Tom Vander Aa, Francisco Barat, G...
163
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VLDB
2004
ACM
152views Database» more  VLDB 2004»
15 years 11 months ago
Balancing energy efficiency and quality of aggregate data in sensor networks
In-network aggregation has been proposed as one method for reducing energy consumption in sensor networks. In this paper, we explore two ideas related to further reducing energy co...
Mohamed A. Sharaf, Jonathan Beaver, Alexandros Lab...
TCAD
2002
104views more  TCAD 2002»
14 years 10 months ago
An instruction-level energy model for embedded VLIW architectures
In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power ...
Mariagiovanna Sami, Donatella Sciuto, Cristina Sil...