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» Compiler Support for Reducing Leakage Energy Consumption
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DAC
2004
ACM
15 years 10 months ago
Leakage aware dynamic voltage scaling for real-time embedded systems
A five-fold increase in leakage current is predicted with each technology generation. While Dynamic Voltage Scaling (DVS) is known to reduce dynamic power consumption, it also cau...
Ravindra Jejurikar, Cristiano Pereira, Rajesh K. G...
VLSID
2008
IEEE
142views VLSI» more  VLSID 2008»
15 years 9 months ago
Temperature and Process Variations Aware Power Gating of Functional Units
Technology scaling has resulted in an exponential increase in the leakage power as well as the variations in leakage power of fabricated chips. Functional units (FUs), like Intege...
Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sar...
DAC
2009
ACM
15 years 10 months ago
NoC topology synthesis for supporting shutdown of voltage islands in SoCs
In many Systems on Chips (SoCs), the cores are clustered in to voltage islands. When cores in an island are unused, the entire island can be shutdown to reduce the leakage power c...
Ciprian Seiculescu, Srinivasan Murali, Luca Benini...
CN
2004
104views more  CN 2004»
14 years 9 months ago
Reducing power consumption and enhancing performance by direct slave-to-slave and group communication in Bluetooth WPANs
Bluetooth is a promising wireless technology aiming at supporting electronic devices to be instantly interconnected into short-range ad hoc networks. The Bluetooth medium access c...
Carlos de M. Cordeiro, Sachin Abhyankar, Dharma P....
ISLPED
2006
ACM
105views Hardware» more  ISLPED 2006»
15 years 3 months ago
Reducing power through compiler-directed barrier synchronization elimination
Interprocessor synchronization, while extremely important for ensuring execution correctness, can be very costly in terms of both power and performance overheads. Unfortunately, m...
Mahmut T. Kandemir, Seung Woo Son