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» Compiler Support for Reducing Leakage Energy Consumption
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MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
14 years 9 months ago
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potentia...
Nam Sung Kim, Krisztián Flautner, David Bla...
ICCAD
2003
IEEE
221views Hardware» more  ICCAD 2003»
15 years 6 months ago
Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems
Abstract— Dynamic voltage scaling (DVS) is a powerful technique for reducing dynamic power consumption in a computing system. However, as technology feature size continues to sca...
Le Yan, Jiong Luo, Niraj K. Jha
ICCAD
2008
IEEE
200views Hardware» more  ICCAD 2008»
14 years 3 months ago
Accurate Equivalent Energy Breakeven Time Estimation for Power Gating
Run-time Power Gating (RTPG) is a recent technique, which aims at aggressively reducing leakage power consumption. Energy breakeven time (EBT), or equivalent sleep time has been pr...
Hao Xu, Wen-Ben Jone, Ranga Vemuri
IPPS
2008
IEEE
15 years 3 months ago
Enhancing the effectiveness of utilizing an instruction register file
This paper describes the outcomes of the NSF Grant CNS-0615085: CSR-EHS: Enhancing the Effectiveness of Utilizing an Instruction Register File. We improved promoting instructions ...
David B. Whalley, Gary S. Tyson
IEEEPACT
2002
IEEE
15 years 2 months ago
Application Transformations for Energy and Performance-Aware Device Management
Energy conservation without performance degradation is an important goal for battery-operated computers, such as laptops and hand-held assistants. In this paper we determine the p...
Taliver Heath, Eduardo Pinheiro, Jerry Hom, Ulrich...