25 search results - page 3 / 5 » Compiler Supports and Optimizations for PAC VLIW DSP Process... |
CODES
2001
IEEE
13 years 10 months ago
2001
IEEE
The paper proposes a novel software-pipelining algorithm, Register Sensitive Force Directed Retiming Algorithm (RSFDRA), suitable for optimizing compilers targeting embedded VLIW ...
ASPDAC
2004
ACM
13 years 11 months ago
2004
ACM
— The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting their special architecture features. Beside the ...
PLDI
2003
ACM
13 years 11 months ago
2003
ACM
Clustered architectures are a solution to the bottleneck of centralized register files in superscalar and VLIW processors. The main challenge associated with clustered architectu...
ASPLOS
1989
ACM
13 years 10 months ago
1989
ACM
A very long instruction word (VLIW) processorexploits parallelism by controlling multiple operations in a single instruction word. This paper describes the architecture and compil...
CASES
2001
ACM
13 years 10 months ago
2001
ACM
Although retargetability has been a major design concern for many compilers, retargetability is a vitally important issue for Digital Signal Processors(DSPs) because the architect...