Sciweavers

1008 search results - page 114 / 202
» Compiler Technology for Two Novel Computer Architectures
Sort
View
118
Voted
ICCAD
2008
IEEE
97views Hardware» more  ICCAD 2008»
15 years 9 months ago
Integrated code and data placement in two-dimensional mesh based chip multiprocessors
— As transistor sizes continue to shrink and the number of transistors per chip keeps increasing, chip multiprocessors (CMPs) are becoming a promising alternative to remain on th...
Taylan Yemliha, Shekhar Srikantaiah, Mahmut T. Kan...
ICCAD
2005
IEEE
147views Hardware» more  ICCAD 2005»
15 years 9 months ago
NoCEE: energy macro-model extraction methodology for network on chip routers
In this paper we present NoCEE, a fast and accurate method for extracting energy models for packet-switched Network on Chip (NoC) routers. Linear regression is used to model the r...
Jeremy Chan, Sri Parameswaran
111
Voted
RTAS
2005
IEEE
15 years 6 months ago
Bounding Worst-Case Data Cache Behavior by Analytically Deriving Cache Reference Patterns
While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and partic...
Harini Ramaprasad, Frank Mueller
86
Voted
EICS
2010
ACM
15 years 5 months ago
Collaboratively maintaining semantic consistency of heterogeneous concepts towards a common concept set
In e-business, creating a common concept set for business integration, interoperation and interaction has to consider the heterogeneity reality of different interpretations from m...
Jingzhi Guo, Iok Ham Lam, Chun Chan, Guangyi Xiao
80
Voted
DAC
2009
ACM
16 years 1 months ago
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications
Power consumption of system-level on-chip communications is becoming more significant in the overall system-on-chip (SoC) power as technology scales down. In this paper, we propos...
Renshen Wang, Nan-Chi Chou, Bill Salefski, Chung-K...