1008 search results - page 53 / 202 » Compiler Technology for Two Novel Computer Architectures |
VLSID
2005
IEEE
15 years 10 months ago
2005
IEEE
A novel topology for Translinear (TL) loops comprising of CMOS Second Generation Current Conveyors (CC-II) and diodes is proposed. The proposed methodology opens a new paradigm to...
HPCA
2005
IEEE
15 years 10 months ago
2005
IEEE
The issue logic of a superscalar processor dissipates a large amount of static and dynamic power. Furthermore, its power density makes it a hot-spot requiring expensive cooling sy...
DSN
2006
IEEE
15 years 3 months ago
2006
IEEE
The advent of deep sub-micron technology has exacerbated reliability issues in on-chip interconnects. In particular, single event upsets, such as soft errors, and hard faults are ...
112
click to vote
WWW
2008
ACM
15 years 10 months ago
2008
ACM
Recent technology trends in the Web Services (WS) domain indicate that a solution eliminating the presumed complexity of the WS-* standards may be in sight: advocates of REpresent...
110
click to vote
GLVLSI
2009
IEEE
15 years 4 months ago
2009
IEEE
In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a...