1008 search results - page 53 / 202 » Compiler Technology for Two Novel Computer Architectures |
87
Voted
VLSID
2005
IEEE
16 years 1 months ago
2005
IEEE
A novel topology for Translinear (TL) loops comprising of CMOS Second Generation Current Conveyors (CC-II) and diodes is proposed. The proposed methodology opens a new paradigm to...
88
Voted
HPCA
2005
IEEE
16 years 1 months ago
2005
IEEE
The issue logic of a superscalar processor dissipates a large amount of static and dynamic power. Furthermore, its power density makes it a hot-spot requiring expensive cooling sy...
112
Voted
DSN
2006
IEEE
15 years 6 months ago
2006
IEEE
The advent of deep sub-micron technology has exacerbated reliability issues in on-chip interconnects. In particular, single event upsets, such as soft errors, and hard faults are ...
135
Voted
WWW
2008
ACM
16 years 1 months ago
2008
ACM
Recent technology trends in the Web Services (WS) domain indicate that a solution eliminating the presumed complexity of the WS-* standards may be in sight: advocates of REpresent...
136
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GLVLSI
2009
IEEE
15 years 7 months ago
2009
IEEE
In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a...