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» Compiler Technology for Two Novel Computer Architectures
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ISLPED
1995
ACM
112views Hardware» more  ISLPED 1995»
15 years 1 months ago
Ultra-low-power analog associative memory core using flash-EEPROM-based programmable capacitors
Analog techniques can lead to ultra-efficient computational systems when applied to the right applications. The problem of associative memory is well suited to array-based analog ...
Alan Kramer, Roberto Canegallo, Mauro Chinosi, D. ...
ECRTS
2000
IEEE
15 years 2 months ago
Towards validated real-time software
We present a tool for the design and validation of embedded real-time applications. The tool integrates two approaches, the use of the synchronous programming language ESTEREL for...
Valérie Bertin, Michel Poize, Jacques Pulou...
NIPS
1998
14 years 11 months ago
Scheduling Straight-Line Code Using Reinforcement Learning and Rollouts
The execution order of a block of computer instructions can make a difference in its running time by a factor of two or more. In order to achieve the best possible speed, compiler...
Amy McGovern, J. Eliot B. Moss
APCSAC
2000
IEEE
15 years 1 months ago
Dataflow Java: Implicitly Parallel Java
Dataflow computation models enable simpler and more efficient management of the memory hierarchy - a key barrier to the performance of many parallel programs. This paper describes...
Gareth Lee, John Morris
VMV
2004
183views Visualization» more  VMV 2004»
14 years 11 months ago
CGiS, a new Language for Data-parallel GPU Programming
In the last few years, GPUs have become new, promising targets for general purpose programming. Their inherent parallel architecture makes them particularly suited for scientific ...
Nicolas Fritz, Philipp Lucas, Philipp Slusallek