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» Compiler Technology for Two Novel Computer Architectures
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ASAP
2003
IEEE
107views Hardware» more  ASAP 2003»
15 years 6 months ago
Energy Aware Register File Implementation through Instruction Predecode
The register file is a power-hungry device in modern architectures. Current research on compiler technology and computer architectures encourages the implementation of larger dev...
José L. Ayala, Marisa Luisa López-Va...
HPCA
2003
IEEE
16 years 1 months ago
Evaluating the Impact of Communication Architecture on the Performability of Cluster-Based Services
We consider the impact of different communication architectures on the performability (performance + availability) of cluster-based servers. In particular, we use a combination of ...
Kiran Nagaraja, Neeraj Krishnan, Ricardo Bianchini...
92
Voted
IPPS
2002
IEEE
15 years 5 months ago
Massively Parallel Solutions for Molecular Sequence Analysis
In this paper we present new approaches to high performance protein database scanning on two novel massively parallel architectures to gain supercomputer power at low cost. The ...
Bertil Schmidt, Heiko Schröder, Manfred Schim...
120
Voted
IEEEPACT
2006
IEEE
15 years 6 months ago
Fast, automatic, procedure-level performance tuning
This paper presents an automated performance tuning solution, which partitions a program into a number of tuning sections and finds the best combination of compiler options for e...
Zhelong Pan, Rudolf Eigenmann
CLEF
2003
Springer
15 years 6 months ago
Regular Sound Changes for Cross-Language Information Retrieval
The aim of this project is the automatic conversion of query terms in one language into their equivalents in a second, historically related, language, so that documents in the sec...
Michael P. Oakes, Souvik Banerjee