1008 search results - page 85 / 202 » Compiler Technology for Two Novel Computer Architectures |
130
Voted
ICDIM
2010
IEEE
15 years 1 months ago
2010
IEEE
One issue for context-aware applications is to identify without delay situations requiring reactions. The identification of these situations is computed from both dynamic context ...
110
Voted
HIPC
2000
Springer
15 years 7 months ago
2000
Springer
Within two or three technology generations, processor architects will face a number of major challenges. Wire delays will become critical, and power considerations will temper the ...
139
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MIDDLEWARE
2005
Springer
15 years 9 months ago
2005
Springer
The overwhelming success of mobile devices and wireless communications is stressing the need for the development of mobility-aware services. Device mobility requires services adap...
133
Voted
DAC
2001
ACM
16 years 4 months ago
2001
ACM
This paper presents LOTTERYBUS, a novel high-performance communication architecture for system-on-chip (SoC) designs. The LOTTERYBUS architecture was designed to address the follo...
127
Voted
VLSID
2000
IEEE
15 years 7 months ago
2000
IEEE
This paper presents a novel system performance analysis technique to support the design of custom communication architectures for System-on-Chip ICs. Our technique fills a gap in...