1141 search results - page 129 / 229 » Compiler-Directed Performance Model Construction for Paralle... |
IEEEPACT
2007
IEEE
15 years 7 months ago
2007
IEEE
Continued scaling of CMOS technology to smaller transistor sizes makes modern processors more susceptible to both transient and permanent hardware faults. Circuitlevel techniques ...
127
Voted
SASP
2009
IEEE
15 years 7 months ago
2009
IEEE
— As growing power dissipation and thermal effects disrupted the rising clock frequency trend and threatened to annul Moore’s law, the computing industry has switched its route...
107
Voted
ICS
2009
Tsinghua U.
15 years 7 months ago
2009
Tsinghua U.
In this work, we propose a new FPGA design flow that combines the CUDA programming model from Nvidia with the state of the art high-level synthesis tool AutoPilot from AutoESL, to...
101
Voted
PLDI
2003
ACM
15 years 6 months ago
2003
ACM
We compile Nova, a new language designed for writing network processing applications, using a back end based on integer-linear programming (ILP) for register allocation, optimal b...
103
Voted
PLDI
2009
ACM
15 years 7 months ago
2009
ACM
It is often impossible to obtain a one-size-fits-all solution for high performance algorithms when considering different choices for data distributions, parallelism, transformati...