1141 search results - page 170 / 229 » Compiler-Directed Performance Model Construction for Paralle... |
108
Voted
ICASSP
2008
IEEE
15 years 7 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
128
click to vote
ICA3PP
2010
Springer
15 years 5 months ago
2010
Springer
Abstract. Finite volume numerical methods have been widely studied, implemented and parallelized on multiprocessor systems or on clusters. Modern graphics processing units (GPU) pr...
151
click to vote
HPDC
2011
IEEE
14 years 4 months ago
2011
IEEE
We investigate proactive dynamic load balancing on multicore systems, in which threads are continually migrated to reduce the impact of processor/thread mismatches to enhance the ...
70
Voted
ISCA
1997
IEEE
15 years 4 months ago
1997
IEEE
DataScalar architectures improve memory system performance by running computation redundantly across multiple processors, which are each tightly coupled with an associated memory....
121
click to vote
APSEC
1996
IEEE
15 years 4 months ago
1996
IEEE
Explosive increase in end-user computing on distributed systems requires that end-users develop application software by themselves. One solution is given as aformula of "adom...